Generally, semiconductor memory devices for storing data are classified into volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory devices lose their data at power-off, and the nonvolatile semiconductor memory devices maintain their data even at power-off. Therefore, the nonvolatile semiconductor memory devices have been widely used at applications in which power can be interrupted suddenly.
The nonvolatile semiconductor memory devices comprise electrically erasable and programmable ROM cells which are referred to as "flash EEPROM cells." Commonly, a flash EEPROM cell, as illustrated in FIG. 1, has a semiconductor substrate (or bulk) 2 of a first conductive type (e.g., P type), source and drain regions 3 and 4 of a second conductive type (e.g., N type) spaced apart relative to each other, a floating gate 6 storing charges and placed over a channel region between the source and drain regions 3 and 4, and a control gate 8 placed over the floating gate 6. Operation of the flash EEPROM cell includes program, erase and read operations.
The program operation of the flash EEPROM cell is performed by biasing the drain region 4 with a positive voltage (e.g., 5V-6V) and the control gate 8 with high voltage (e.g., 10V). At this time, the source region 3 and the bulk 2 are grounded. In the case where charges stored in the floating gate 6 doesn't exist, the bias voltages cause an inversion-layer channel of charges to be formed on a surface of the bulk 2 between the source and drain regions 3 and 4. As is well known to ones skilled in the art, the drain-source voltage accelerates charges into the drain region through the inversion-layer channel. Charges thus accelerated gain very high kinetic energy and are named "hot electrons". The hot electrons are accumulated on the floating gate 6 via a mechanism which is referred to as hot electron injection.
As is well known to ones skilled in the art, as a large amount of charges accumulate on the floating gate, the effective threshold voltage (V.sub.th) of a cell transistor is increased. As the effective threshold voltage is increased in a range of about 6V to 7V, the cell transistor enters a nonconductive state (i.e., off state) when a read voltage is applied to the control gate during a read operation. In a state known as a program state, the flash EEPROM cell stores logic `0` (or logic `1` depending on the program mask). Once programmed, the flash EEPROM cell maintains its effective threshold voltage even at power-off.
The erase operation of the flash EEPROM cell is performed by eliminating charges stored in the floating gate. The flash EEPROM cell is erased, for example, by applying a negative high voltage (e.g., -10V) to the control gate 8 and a positive voltage (e.g., +6V) to the bulk 2. At this time, the source and drain regions 3 and 4 are maintained at a floating state of high-impedance. By such a bias condition, an electric field of about 6-7 MV/cm is formed across a tunneling oxide layer 5 which has a thickness of about 100 A, and negative charges accumulated in the floating gate 6 are emitted via the tunneling oxide layer 5 to the bulk 2 via a mechanism such as Fowler-Nordheim tunneling. This makes the effective threshold voltage of the cell transistor be reduced to within a range of about 1V to 3V. As its effective threshold voltage is reduced, the cell transistor enters a conductive state (i.e., on state) when a read voltage is applied to the control gate during a read operation. In a state known as an erase state, the flash EEPROM cell stores logic `1` (or logic `0` if no logic inversion).
The read operation of the flash EEPROM cell is performed by applying a read voltage (e.g., 4.5V) to a control gate 8 through a word line and a positive bias voltage (e.g., 1V) to a drain region 4 through a bit line. If programmed, the flash EEPROM cell doesn't conduct cell current, and the bit line connected to the cell is maintained at the bias voltage of 1V. If not programmed (or if erased), the EEPROM cell conducts cell current (e.g., 30 .mu.A), and the bit line connected thereto is grounded. Therefore, by sensing a bit line voltage (current), the data state (or programmed state) of the flash EEPROM cell (logic `1` or logic `0`) may be determined.
As above described, the program operation requires a high voltage which has a voltage level higher than a power supply voltage level. A high voltage generating circuit (or a voltage pumping circuit) for generating the high voltage is disclosed in U.S. Pat. No. 5,081,371 entitled "INTEGRATED CHARGE PUMP CIRCUIT WITH BACK BIAS VOLTAGE REDUCTION" and U.S. Pat. No. 5,280,420 entitled "CHARGE PUMP WHICH OPERATES ON A LOW VOLTAGE POWER SUPPLY".
A prior art nonvolatile semiconductor memory device with a high voltage generating circuit is illustrated in FIG. 2. In FIG. 2, a memory cell array 11 comprises NOR-structured nonvolatile memory cells (flash EEPROM cells) arranged in a matrix form of rows and columns, plural word lines extending along the rows, and plural bit lines extending along the columns. Such an array 11 of NOR-structured memory cells is disclosed in U.S. Pat. No. 5,680,349 entitled "NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ROW DECODER SUPPLYING A NEGATIVE POTENTIAL TO WORD LINES DURING ERASE MODE" and U.S. Pat. No. 5,511,026 entitled "BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES", which are hereby incorporated by reference.
As illustrated in FIG. 2, an address buffer circuit 12, a row decoder circuit (X-Decoder) 13, a column decoder circuit (Y-Decoder)14, a column pass gate circuit (Y-Gating) 15 and a write driver circuit 16 are further provided in the memory device 10. Since the above-mentioned constituent elements are well known in the art, further description thereof is omitted. Furthermore, the nonvolatile semiconductor memory device 10 comprises a command register 17, a program controller 18, a high voltage generating circuit 21 consisting of first and second high voltage generators 19 and 20, and a timer 22. The constituent elements will be explained with reference to FIG. 3 which shows a timing diagram for describing a program operation according to the prior art.
When the program operation for the memory cells is required, external command codes defined by address signals XAi and data DQi are continuously inputted to the command register 17 in synchronism with a write enable signal WEB, so that the memory device 10 enters a program mode. The command register 17 generates a program enable signal PGM indicating the program operation in response to the command codes (i.e., address signals and data), and the program controller 18 responds to the program enable signal PGM to generate a high voltage enable signal VPP.sub.-- en for activating the high voltage generating circuit 21. Next, the row decoder circuit 13 selects a word line associated with a row address which is applied through the address buffer circuit 12, and the column decoder circuit 14 and the column pass gate circuit 15 select bit lines associated with a column address which is applied through the address buffer circuit 12.
As shown in FIG. 3, when a high voltage enable signal VPP.sub.-- en from the program controller 18 transitions from a logic low level to a logic high level in synchronism with a low-to-high transition of the signal PGM, the first and second high voltage generators 19 and 20 start to generate high voltages VPP1 and VPP2 each of which is higher than the power supply voltage. The first high voltage VPP1 is a voltage of about 10V which is supplied to a selected word line through the row decoder circuit 13, and is hereinafter referred to as a word line voltage. The second high voltage VPP2 is a voltage of about 5V which is supplied to a selected bit line through the column pass gate circuit 15 via the write driver circuit 16, and is hereinafter referred to as a bit line voltage). At the same time, an output pulse signal C from the timer 22 is activated high when the high voltage enable signal VPP.sub.-- en changes from a logic low level to a logic high level, and then is inactivated low after a predetermined time (corresponding to a time in which the high voltages VPP1 and VPP2 are pumped up to their required voltages) elapses. The program controller 18 generates a control signal PGMBL for controlling the write driver circuit 16 when the output pulse signal C from the timer 22 transitions from high to low. This leading edge of PGMBL forces the write driver circuit 16 to drive the selected bit line according to a data state to be programmed. After a time elapses (a selected memory cell is programmed), the control signal PGMBL is inactivated low by the program controller 18.
As above described, the prior art memory device 10 in FIG. 2 has the timer 22 for generating the output pulse signal C to be activated during a predetermined time so as to determine a time when the high voltage VPP2 is applied to a selected bit line. The duration of enable period t.sub.A of the output pulse signal C may be determined--by testing, e.g. a circuit simulation, a time when the high voltage generating circuit 21 generates the high voltages VPP1 and VPP2 with a required voltage level considering various power supply voltages in accordance with applied fields. As is well known to those skilled in the art, a high voltage generator using higher power supply voltage generates voltage more rapidly than one using lower power supply voltage. Therefore, the enable period t.sub.A of the output pulse signal C may be determined on the basis of the high voltage generator using the lower power supply voltage.
According to the above description, the enable period t.sub.A of the output pulse signal C, which is implemented in the memory device using the higher power supply voltage, is determined by the timer 22 which is implemented in the memory device using the lower power supply voltage. That is, a point in time of a high-to-low transition of the signal C at the higher power supply voltage is limited by that at the lower power supply voltage. For this reason, a loss of total program time of the memory device using the higher power supply voltage is inevitable.